In many present day wireless communication applications, a digital synthesizer is used and often implemented by way of a digital phase locked loop (DPLL) that is used to control a digitally controlled oscillator (DCO) to generate (often referred to as ‘synthesize’) an output radio frequency (local oscillator) signal. Such digital synthesizers provide the benefit of simplifying the integration of the synthesizer circuitry within large scale integrated digital circuit devices, as compared with equivalent analogue synthesizers, thereby reducing size, cost, power consumption and design complexity. Furthermore, DPLLs intrinsically present lower phase noise than their analogue counterparts.
All-digital phase locked loops (ADPLLs) can be used as a frequency synthesizer in radio frequency circuits to create a stable local oscillator for transmitters or receivers, due to their low power consumption and high integration level. They can also be used to generate the frequency-modulated continuous wave (FMCW) waveforms required by a radar transmitter.
Modern FMCW radar systems require fast modulation ramps (with ramp-up times from 10 us to 100 us), but only process radar signals during ramp-up periods. A modulation ramp is a linear frequency-modulated continuous-wave signal with frequency varying over time. The modulation occurs during ramp up and ramp down with various slopes to allow processing of the received signal in order to extract range and speed information of targets. As the ramp-up time (from a start frequency to a stop frequency) is used for radar processing, the reset time, namely the time taken for the ADPLL to reset to the start frequency, is an unused (and therefore wasted) time. Hence, the inventors have recognized and appreciated that it is important in the design of ADPLL circuits, particularly ADPLL circuits for FMCW radar applications, that this reset time is kept as short as possible in order to speed up the time between successive ramps. This reset time is limited by the PLL bandwidth, which cannot be set too wide in order to ensure good phase-noise. This is a similar performance limitation as found in analog and other digital PLLs.
U.S. Pat. No. 7,498,890 B2 describes a continuous reversible gear shifting mechanism for an ADPLL. However, the algorithm in U.S. Pat. No. 7,498,890 B2 uses gear-shifting inside a loop filter in an ADPLL, and is only notably used in order to speed up a PLL lock time. Thus, and notably, the reversible gear shifting mechanism is switched off after locking, as it creates DCO frequency jumps at each gear shift, which is undesirable in most applications. A further disadvantage of the continuous reversible gear shifting mechanism of U.S. Pat. No. 7,466,207 B2 is that it is only able to support decreasing loop gains, i.e. from a large gain to a small gain.
Accordingly, it is important to generate modulation signals for FMCW with very short (i.e. wasted) reset time, thereby supporting a faster refresh rate (e.g. successive resets to the start frequency) of the radar device or radar-supported device.